MAX5950ETJ+【PDF 21/28 页】IC PWM CTRL HOT-SW 12V 32TQFN-EP

12V PWM Controller with Hot-Swap

______________________________________________________________________________________ 21

quency is higher than f

LC

, but lower than the closed-

loop crossover frequency. The equations that define

the error amplifiers poles and zeroes (f

Z1

, f

Z2

, f

P1

, f

P2

,

and f

P3

) are the same as before. However, f

P2

is now

lower than the closed-loop crossover frequency. Figure

7 shows the error-amplifier feedback, as well as its gain

response for circuits that use higher ESR output capac-

itors (tantalum, aluminum electrolytic, etc.)

Pick a value for feedback resistor R5 in Figure 7 (values

between 1k& and 10k& are adequate). C7 is then cal-

culated as:

The circuit is implemented with C7 >> C8 and R3 >>

R6, in which case the error-amplifier gain between f

P2

and f

P3

is approximately equal to:

The modulator gain at f

C

is:

Since G

EA(fC)

x G

MOD(fC)

= 1, R6 can then be calculat-

ed as:

f

P2

is set to f

ZESR

. C6 is then calculated as:

R3 is then calculated as:

f

P3

is set at 5xf

C

. Therefore, C8 is calculated as:

Hot-Swap Controller

Applications Information

Additional External Gate Capacitance

External capacitance can be added from the gate of the

external MOSFET to AGND to reduce the dv/dt of the

PWM controller input voltage (V

PWM_IN

), decreasing the

hot-swap inrush current. Add a 10k& resistor in series

with the added gate capacitor to prevent degrading the

device turn-off response to a fault condition.

Layout Considerations

To take advantage of the switch response time to an

output fault condition, it is important to keep all traces as

short as possible and to maximize the high-current trace

width to reduce the effect of undesirable parasitic

inductance. Use a ground plane to minimize impedance

and inductance. Minimize the trace length that connects

to IN and HSENSE (< 10mm), and ensures accurate

current sensing with Kelvin connections.

When the output is short circuited, the voltage drop

across the external MOSFET becomes large. Hence,

the power dissipation in the switch increases, as does

the die temperature. An efficient way to achieve good

power dissipation on a surface-mount package is to lay

out two copper pads directly under the MOSFET pack-

age on both sides of the board. Connect the two pads

to the ground plane through vias, and use enlarged

copper mounting pads on the top side of the board.

PWM Controller

Applications Information

Power Dissipation

The 32-pin TQFN thermally enhanced package can dis-

sipate 2.7W. Calculate power dissipation in the

MAX5950 as a product of the input voltage and the

total REG output current (I

REG

). I

REG

includes quies-

cent current (I

Q

) and gate-drive current (I

DREG

):

P

D

= V

IN

x I

REG

I

REG

= I

Q

+ [f

SW

x (Q

G1

+ Q

G2

)]

where Q

G1

and Q

G2

represent the total gate charge of

the low-side and high-side external MOSFETs, f

SW

is the

switching frequency of the converter, and I

Q

is the quies-

cent current of the device at the switching frequency.

Use the following equation to calculate the maximum

power dissipation (P

DMAX

) in the chip at a given ambi-

ent temperature (T

A

):

P

DMAX

= 34.5 x (150 - T

A

)&&&.mW

C

R

f

C

8

1

2

5 5

=

?nbsp ?nbsp ?/DIV>

?/DIV>

R

f

C

LC

3

1

2

6

H

?nbsp ?/DIV>

?/DIV>

C

ESR

R

OUT

6

=

?/DIV>

R

R G

L C

f

MOD DC

OUT

C

6

5

2

H

?/DIV>

?nbsp ?/DIV>

?/DIV>

( )

?/DIV>

G

L C

f

MOD fC

MOD DC

OUT C

( )

=

?nbsp ?/DIV>

?/DIV>

2

?/DIV>

R

5

f

R

LC

7

1

2 0 5

5

=

?nbsp ?nbsp ?/DIV>

?nbsp .

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